The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include sequential deposition of conductive and insulative layers on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove material from one or more conducting layers from the areas not covered by the mask, thereby etching the conducting layer or layers in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. Additional techniques, such as dual damascene processes, are used to form conductive vias which establish electrical contact between vertically-spaced conductive lines or layers in the circuits. The finished semiconductor product includes microelectronic devices including transistors, capacitors and resistors that form the integrated circuits on each of multiple die on a single wafer.
In the semiconductor industry, CMOS (complementary metal-oxide semiconductor) technology is extensively used in the fabrication of IC devices. CMOS technology typically involves the use of overlying layers of semiconductor material with the bottom layer being a dielectric layer and the top layer being a layer of doped silicon material that serves as a low- resistivity electrical contact gate electrode. The gate electrode, also referred to as a gate stack, typically overlies the dielectric layer.
In the semiconductor fabrication industry, silicon oxide (SiO2) is frequently used for its insulating properties as a gate oxide or dielectric. As the dimensions of device circuits on substrates become increasingly smaller, the gate dielectric thickness must decrease proportionately in field effect transistors (FETs) to approximately 3 to 3.5 nonometers. Accordingly, device performance and reliability can be adversely affected by such factors as interfacial defects, defect precursors and diffusion of dopants through gate dielectrics, as well as unintended variations in thickness in the gate oxide layer among central and peripheral regions of the layer.
Two types of CMOS device structures which are commonly fabricated in semiconductor technology include the MOSCAP (metal oxide semiconductor capacitor) structure and the MOSFET (metal oxide semiconductor field effect transistor) structure. Both of these structures include a substrate on which is deposited a dielectric layer having a high dielectric constant (k), such as a pad oxide layer. A silicon-containing gate, or gate stack, is deposited on the dielectric layer and connects a pair of trench oxide layers (in the case of a MOSCAP structure) or source and drain regions (in the case of a MOSFET structure).
One gate stack fabrication technique involves the deposition of polycrystalline silicon (polysilicon) on the high-k dielectric layers of multiple substrates simultaneously in a vertical process furnace to form the gate stack on each substrate. Such a deposition process requires a relatively high thermal budget (620 degrees C. at a process time of typically about 1.5 hours). Another technique involves the deposition of amorphous silicon on the dielectric layer in a process furnace to form the gate stack on each of the multiple substrates. Compared to the polysilicon deposition process, the deposition of amorphous silicon has a lower thermal budget (550 degrees C. at a process time of typically about 2 hours). Therefore, due to the relatively lower thermal budget of the amorphous silicon deposition process in the furnace processing of multiple substrates, amorphous silicon has a higher stability than polysilicon when deposited as a gate stack on a dielectric layer having a high dielectric constant.
Formation of a gate stack on a pad oxide layer in fabrication of both the MOSCAP and MOSFET structures is currently carried out typically on single substrates using chemical vapor deposition (CVD) in a CVD process chamber. In the fabrication of MOSCAP and MOSFET structures, polysilicon or amorphous silicon is deposited on a high-k dielectric layer in a CVD process chamber. Polysilicon is deposited on the dielectric layer at a temperature of typically about 675 degrees C. for a process time of about 1 minutes. Amorphous silicon, on the other hand, is deposited on the dielectric layer at a temperature of typically about 575 degrees C. for about 10 min. This is accomplished by reacting hafnium dioxide (HfO2) with silicon (Si) to form silicon oxides (SiOx), according to the following equation:HfO2+Si-Δ→HfO2-x+SiOx
Ideally, the silicon oxides are deposited in an even layer over the high-k dielectric layer to form the high-stability gate stack structure. However, it has been found that in spite of the lower thermal budget of the amorphous silicon deposition process, the amorphous silicon is less stable than the polysilicon in single-wafer processing applications due to unintended chemical reactions between the hafnium dioxide and cleaning agent used to clean the process chamber.
During gate stack fabrication or other extended use of the CVD chamber in semiconductor fabrication, some of the silicon oxide or other high molecular weight residues accumulate on the interior surfaces of the process chamber. Because these residues are loosely attached to the chamber wall interior surfaces, the residues have a tendency to break off and contaminate device structures being fabricated on the wafer. Accordingly, at regular intervals, the CVD process chamber must be subjected to a chamber-cleaning procedure to remove the residues of silicon oxides from the interior chamber walls.
To prevent accumulation of excessive quantities of residues inside a CVD chamber, the chamber is dry-cleaned after a predetermined period of operation such that micro-particles attached to the interior sidewalls of the chamber are removed. After longer periods of operation, preventative maintenance (PM) of the chamber is carried out to restore the reaction chamber to ideal operating conditions.
Even after regular dry-cleaning and PM cleanings of the CVD chamber are carried out, some residual particles frequently remain attached to the interior surfaces of the chamber. Accordingly, a novel chamber seasoning method is needed to provide a seasoning film on the interior surfaces of a CVD chamber in order to minimize the accumulation of residual particles in the chamber during chemical vapor deposition processes.
An object of the present invention is to provide a novel method for the seasoning of a process chamber in such a manner as to enhance the quality of device features fabricated on substrates in the chamber.
Another object of the present invention is to provide a novel chamber seasoning method which includes providing a seasoning film on the interior surfaces of a process chamber to prevent the excessive accumulation of particles in the chamber.
Still another object of the present invention is to provide a novel chamber cleaning method which is particularly adapted for a CVD chamber but may be adapted to a variety of process chambers for a variety of semiconductor fabrication or other processes.
Yet another object of the present invention is to provide a novel chamber cleaning method which improves the stability of films deposited on a substrate.
A still further object of the present invention is to provide a novel chamber seasoning method which may be carried out after a chamber-cleaning process and includes deposition of an oxygen-rich seasoning film on the interior surfaces of a CVD chamber.
Another object of the present invention is to provide a novel chamber seasoning method which is effective in reducing the quantity of defects in devices fabricated on a wafer and increasing the WAT (wafer acceptance testing) yield.